| Published Papers |
| No. | Ｔitle | Journal | Vol | No | Start Page | End Page | Publication date | DOI | Referee |
| 1 | Design and Implementation of Energy-Efficient Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic  | IEEE Transactions on Applied Superconductivity | 33 | 5 | 1 | 5 | Aug. 2023 | https://doi.org/10.1109/tasc.2023.32431801 | Refereed |
| 2 | Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E106.A | 5 | 823 | 831 | May. 1, 2023 | https://doi.org/10.1587/transfun.2022gcp00031 | Refereed |
| 3 | Control of Magnetic Resonance Wireless Power Transmission to Multiple Devices Using the SP-PS Coupling Circuit | 2022 Asia-Paci c Microwave Conference (APMC 2022) | 73 | | 67 | 69 | Nov. 2022 | https://doi.org/10.34385/proc.73.we1-f5-41 | Refereed |
| 4 | A Study on the Efficient Design of Adders Using Adiabatic Quantum-Flux-Parametron Circuits | 2022 IEEE 11th Global Conference on Consumer Electronics (GCCE 2022) | | | | | Oct. 2022 | | Refereed |
| 5 | Design and implementation of high-performance Binary Neural Network using Adiabatic Quantum-Flux-Parametron logic | The Applied Super- conductivity Conference 2022(ASC 2022) | | | | | Oct. 2022 | | Refereed |
| 6 | A Study on In-Memory Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic | Proc. 14th Superconducting SFQ VLSI Workshop (SSV 2022) | | | | | Sep. 2022 | | Refereed |
| 7 | A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier | 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 16, 2021 | https://doi.org/10.1109/ispacs51563.2021.96510591 | Refereed |
| 8 | A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology | 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 16, 2021 | https://doi.org/10.1109/ispacs51563.2021.96509761 | Refereed |
| 9 | A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS | 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 16, 2021 | https://doi.org/10.1109/ispacs51563.2021.96510221 | Refereed |
| 10 | Linearity Compensation for Conversion Error in Non-binary and Binary Hybrid ADC | 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 16, 2021 | https://doi.org/10.1109/ispacs51563.2021.96510391 | Refereed |
| 11 | Special section on analog circuit techniques and related topics | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E104A | 2 | 476 | 476 | 2021 | https://doi.org/10.1587/transfun.2020GCF00011 | |
| 12 | Special section on analog circuit techniques and related topics | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E104A | 2 | 476 | 476 | 2021 | https://doi.org/10.1587/transfun.2020GCF00011 | |
| 13 | Input bias current reduction technique for operational amplifier in a standard CMOS technology | Electronics and Communications in Japan | 103 | 7 | 30 | 36 | Jul. 2020 | https://doi.org/10.1002/ecj.122421 | Refereed |
| 14 | Input bias current reduction technique for operational amplifier in a standard CMOS technology | IEEJ Transactions on Electronics, Information and Systems | 140 | 1 | 9 | 15 | Jan. 1, 2020 | https://doi.org/10.1541/ieejeiss.140.91 | Refereed |
| 15 | Special section on analog circuits and their application technologies | IEICE Transactions on Electronics | E103.C | 10 | 445 | 445 | 2020 | https://doi.org/10.1587/transele.2019CTF00011 | |
| 16 | Special section on analog circuits and their application technologies | IEICE Transactions on Electronics | E103.C | 10 | 445 | 445 | 2020 | https://doi.org/10.1587/transele.2019CTF00011 | |
| 17 | A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology | 2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Dec. 2019 | https://doi.org/10.1109/ispacs48206.2019.89863711 | Refereed |
| 18 | Analog / Mixed-Signal / RF Circuits for Complex Signal Processing | 2019 IEEE 13th International Conference on ASIC (ASICON) | | | | | Oct. 2019 | https://doi.org/10.1109/asicon47005.2019.89835481 | Refereed |
| 19 | Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase | IEICE Electronics Express | 16 | 12 | 20190280 | 20190280 | Jun. 2019 | https://doi.org/10.1587/elex.16.201902801 | Refereed |
| 20 | A 6th-order quadrature bandpass delta sigma AD modulator using dynamic amplifier and noise coupling SAR quantizer | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E102A | 3 | 507 | 517 | Mar. 1, 2019 | https://doi.org/10.1587/transfun.E102.A.5071 | Refereed |
| 21 | Area reduction technique for digital circuit part in non-binary analog-to-digital converter | IEEJ Transactions on Electronics, Information and Systems | 139 | 1 | 76 | 82 | Jan. 1, 2019 | https://doi.org/10.1541/ieejeiss.139.761 | Refereed |
| 22 | A 720uW 77.93dB SNDR ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase | 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 2018 | https://doi.org/10.1109/ispacs.2018.89233961 | Refereed |
| 23 | A 6th-Order Complex Bandpass $\Delta\Sigma \text{AD}$ Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer | 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 2018 | https://doi.org/10.1109/ispacs.2018.89235801 | Refereed |
| 24 | Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC | Analog Integrated Circuits and Signal Processing | 97 | 2 | 207 | 214 | Nov. 2018 | https://doi.org/10.1007/s10470-018-1197-21 | Refereed |
| 25 | Experimental implementation of Δ Σ AD modulator with dynamic analog components | Analog Integrated Circuits and Signal Processing | 97 | 2 | 215 | 223 | Nov. 2018 | https://doi.org/10.1007/s10470-018-1231-41 | Refereed |
| 26 | A noise coupled ΔΣAD modulator using passive adder embedded noise shaping SAR quantizer | IEICE Transactions on Electronics | E101C | 7 | 480 | 487 | Jul. 1, 2018 | https://doi.org/10.1587/transele.E101.C.4801 | Refereed |
| 27 | A 2nd-order ΔΣAD modulator using dynamic analog components with simplified operation phase | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E101A | 2 | 425 | 433 | Feb. 2018 | https://doi.org/10.1587/transfun.E101.A.4251 | Refereed |
| 28 | A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique | 2017 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 2017 | https://doi.org/10.1109/ispacs.2017.82665491 | Refereed |
| 29 | The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC | 2017 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 2017 | https://doi.org/10.1109/ispacs.2017.82665501 | Refereed |
| 30 | Experimental results of reconfigurable non-binary cyclic ADC | 2017 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 2017 | https://doi.org/10.1109/ispacs.2017.82665511 | Refereed |
| 31 | A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode | Proceedings of the 24th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2017 | | | 45 | 49 | Aug. 8, 2017 | https://doi.org/10.23919/MIXDES.2017.80045921 | Refereed |
| 32 | Non-binary cyclic and binary SAR hybrid ADC | 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems | | | | | Jun. 2017 | https://doi.org/10.23919/mixdes.2017.80051631 | Refereed |
| 33 | A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E100.A | 2 | 534 | 540 | Feb. 2017 | https://doi.org/10.1587/transfun.e100.a.5341 | Refereed |
| 34 | Non-binary cyclic ADC with correlated level shifting technique | 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) | | | | | Jan. 2017 | https://doi.org/10.1109/aspdac.2017.78582801 | Refereed |
| 35 | A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components | 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) | | | | | Jan. 2017 | https://doi.org/10.1109/aspdac.2017.78582791 | Refereed |
| 36 | A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer | 2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Oct. 2016 | https://doi.org/10.1109/ispacs.2016.78247251 | Refereed |
| 37 | Leakage current compensation technique of ESD protection circuit for CMOS operational amplifier | 2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Oct. 2016 | https://doi.org/10.1109/ispacs.2016.78247221 | Refereed |
| 38 | A 14-bit 80ksps Cyclic ADC Based on β-expansion | Proceedings of 2016 International Conference on Analog VLSI Circuits, Boston, USA | | | 11 | 15 | Aug. 2016 | | Refereed |
| 39 | Non-Binary and Binary Weighted Hybrid Pipeline ADC with β estimation | Proceedings of 2016 International Conference on Analog VLSI Circuit, Boston, USA | | | 17 | 20 | Aug. 2016 | | Refereed |
| 40 | Experimental Implementation of β-Expansion Cyclic ADC with Correlated Level Shifting Technique | Proceedings of 2016 International Conference on Analog VLSI Circuits, Boston, USA, August 24-26, 2016 | | | 5 | 9 | Aug. 2016 | | Refereed |
| 41 | A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion | 2015 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2015 | | | 294 | 298 | Mar. 11, 2016 | https://doi.org/10.1109/ISPACS.2015.74327831 | Refereed |
| 42 | A 12Bit 200Msps Spilt-Based Pipeline ADC Design | International Journal of Information and Electronics Engineering | 6 | 6 | 337 | 342 | 2016 | https://doi.org/10.18178/ijiee.2016.6.6.6501 | Refereed |
| 43 | A low-distortion delta-sigma modulator with ring amplifier and passive adder embedded SAR quantizer | 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | | | | | Nov. 2015 | https://doi.org/10.1109/ispacs.2015.74327841 | Refereed |
| 44 | Rigorous estimates of quantization error for A/D converters based on beta-map | Nonlinear Theory and Its Applications, IEICE | 6 | 1 | 99 | 111 | 2015 | https://doi.org/10.1587/nolta.6.991 | Refereed |
| 45 | An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components | Proceedings of the IEEE 2014 Custom Integrated Circuits Conference | | | | | Sep. 2014 | https://doi.org/10.1109/cicc.2014.69461231 | Refereed |
| 46 | Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm | IEICE Transactions on Electronics | E97.C | 4 | 308 | 315 | Apr. 2014 | https://doi.org/10.1587/transele.e97.c.3081 | Refereed |
| 47 | Rigorous analysis of quantization error of an A/D converter based on $\beta$-map | 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) | | | | | May. 2013 | https://doi.org/10.1109/iscas.2013.65718571 | Refereed |
| 48 | Robust Cyclic ADC Architecture Based on $\beta$-Expansion | IEICE Transactions on Electronics | E96.C | 4 | 553 | 559 | Apr. 2013 | https://doi.org/10.1587/transele.e96.c.5531 | Refereed |
| 49 | Non-binary Pipeline Analog-to-Digital Converter Based on $\beta$-Expansion | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E96.A | 2 | 415 | 421 | Feb. 2013 | https://doi.org/10.1587/transfun.e96.a.4151 | Refereed |
| 50 | Non-binary SAR ADC with Digital Compensation for Comparator Offset Effects | The IEICE transactions on electronics C | Vol.J94-C | No.3 | 68 | 78 | Mar. 2011 | | Refereed |
| 51 | Non-binary SAR ADC with digital error correction for low power applications | 2010 IEEE Asia Pacific Conference on Circuits and Systems | | | | | Dec. 2010 | https://doi.org/10.1109/apccas.2010.57747471 | Refereed |
| 52 | SAR ADC Architecture with Digital Error Correction | IEEJ Transactions on Electrical and Electronic Engineering | 5 | 6 | 651 | 659 | Nov. 2010 | https://doi.org/10.1002/tee.205881 | Refereed |
| 53 | SAR ADC Algorithm with Redundancy and Digital Error Correction | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E93-A | 2 | 415 | 423 | Feb. 2010 | https://doi.org/10.1587/transfun.e93.a.4151 | Refereed |
| 54 | Noise-Coupled Image Rejection Architecture of Complex Bandpass ΔΣAD Modulator | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E93-A | 2 | 390 | 394 | Feb. 2010 | https://doi.org/10.1587/transfun.e93.a.3901 | Refereed |
| 55 | Study of Q Factor and Loop Delay Effects in a Continuous-Time Bandpass ΔΣAD Modulator | 電子情報通信学会論文誌. A, 基礎・境界 = The transactions of the Institute of Electronics, Information and Communication Engineers. A | Vol.J93-A | No.2 | 107 | 118 | Feb. 2010 | | Refereed |
| 56 | Noise-Coupled ΔΣAD Modulator with Shared OP-Amp | IEEJ Transactions on Electronics, Information and Systems | 129 | 12 | 2167 | 2173 | Dec. 2009 | https://doi.org/10.1541/ieejeiss.129.21671 | Refereed |
| 57 | Study of Q factor and loop delay effects of a continuous-time ΔΣAD modulator | 2009 IEEE 8th International Conference on ASIC | | | | | Oct. 2009 | https://doi.org/10.1109/asicon.2009.53514861 | Refereed |
| 58 | Analysis and design of inverter-type Gm-C bandpass filter | IEEJ Transactions on Electronics, Information and Systems | 129 | 8 | 1483 | 1489 | Aug. 2009 | https://doi.org/10.1541/ieejeiss.129.14831 | Refereed |
| 59 | Complex bandpass $\Delta\Sigma$AD modulator with noise-coupled image rejection | 2009 52nd IEEE International Midwest Symposium on Circuits and Systems | | | | | Aug. 2009 | https://doi.org/10.1109/mwscas.2009.52360801 | Refereed |
| 60 | Cross-Noise-Coupled Architecture of Complex Bandpass ΔΣAD Modulator | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E92-A | 4 | 998 | 1003 | Apr. 2009 | https://doi.org/10.1587/transfun.e92.a.9981 | Refereed |
| 61 | SAR ADC algorithm with redundancy | APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems | | | | | Nov. 2008 | https://doi.org/10.1109/apccas.2008.47460111 | Refereed |
| 62 | $\Delta\Sigma$AD modulator for low power application | APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems | | | | | Nov. 2008 | https://doi.org/10.1109/apccas.2008.47462491 | Refereed |
| 63 | High-resolution DPWM generator for digitally controlled DC-DC converters | APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems | | | | | Nov. 2008 | https://doi.org/10.1109/apccas.2008.47461721 | Refereed |
| 64 | Complex bandpass ΣΔAD modulator with noise-coupled architecture | 2008 51st Midwest Symposium on Circuits and Systems | | | | | Aug. 2008 | https://doi.org/10.1109/mwscas.2008.46168421 | Refereed |
| 65 | High-Resolution DPWM Generator for Digitally Controlled DC-DC Converters | The IEICE transactions on electronics C | Vol.J91-C | No.8 | 418 | 427 | Aug. 2008 | | Refereed |
| 66 | Novel Architecture of Feedforward Second-Order Multibit $\Delta\Sigma$AD Modulator | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E91-A | 4 | 965 | 970 | Apr. 1, 2008 | https://doi.org/10.1093/ietfec/e91-a.4.9651 | Refereed |
| 67 | Second-order ΔΣAD modulator with novel feedforward architecture | 2007 50th Midwest Symposium on Circuits and Systems | | | 148 | 151 | Aug. 2007 | https://doi.org/10.1109/mwscas.2007.44885581 | Refereed |
| 68 | A Second-Order Multibit Complex Bandpass $\Delta\Sigma$AD Modulator with I, Q Dynamic Matching and DWA Algorithm | IEICE Transactions on Electronics | E90-C | 6 | 1181 | 1188 | Jun. 1, 2007 | https://doi.org/10.1093/ietele/e90-c.6.11811 | Refereed |
| 69 | Multi-Band-Pass ΔΣ Modulator Techniques and Their Applications | 電子情報通信学会論文誌. C, エレクトロニクス = The transactions of the Institute of Electronics, Information and Communication Engineers. C | Vol.J90-C | No.2 | 143 | 158 | Feb. 2007 | | Refereed |
| 70 | A 2.8-V Multibit Complex Bandpass $\Delta\Sigma$AD Modulator in 0.18$\mu$m CMOS | 2007 Asia and South Pacific Design Automation Conference | | | | | Jan. 2007 | https://doi.org/10.1109/aspdac.2007.3579581 | Refereed |
| 71 | A Multibit Complex Bandpass $\Delta\Sigma$AD Modulator with I, Q Dynamic Matching and DWA Algorithm | 2006 IEEE Asian Solid-State Circuits Conference | | | 55 | 58 | Nov. 2006 | https://doi.org/10.1109/asscc.2006.3578501 | Refereed |
| 72 | Complex Bandpass $\Delta\Sigma$AD Modulator Architecture without I, Q-Path Crossing Layout | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E89-A | 4 | 908 | 915 | Apr. 1, 2006 | https://doi.org/10.1093/ietfec/e89-a.4.9081 | Refereed |
| 73 | Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths | IEICE Transactions on Electronics | E88-C | 6 | 1290 | 1294 | Jun. 2005 | https://doi.org/10.1093/ietele/e88-c.6.12901 | Refereed |
| 74 | Reducing spurious output of balanced modulators by dynamic matching of I, Q quadrature paths | The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. | | | | | Jul. 2004 | https://doi.org/10.1109/mwscas.2004.13539331 | Refereed |
| 75 | A noise-shaping algorithm of multi-bit DAC nonlinearities in complex bandpass Delta Sigma AD modulators | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | E87.A | 4 | 792 | 800 | Apr. 2004 | | Refereed |
| 76 | An element rotation algorithm for multi-bit DAC nonlinearities in complex bandpass ΔΣAD modulators | 17th International Conference on VLSI Design. Proceedings | 1 | | 151 | 156 | Jan. 2004 | https://doi.org/10.1109/icvd.2004.12609171 | Refereed |
| 77 | High-speed CMOS track/hold circuit design | Analog Integrated Circuits and Signal Processing | 27 | 1-2 | 165 | 176 | Apr. 2001 | https://doi.org/10.1023/a:10112836138691 | Refereed |
| 78 | Highly-Efficient Low-Voltage-Operation Charge Pump Circuits Using Bootstrapped Gate Transfer Switches | IEEJ Transactions on Electronics, Information and Systems | 120 | 10 | 1339 | 1345 | Oct. 2000 | https://doi.org/10.1541/ieejeiss1987.120.10_13391 | Refereed |
| 79 | A high-speed CMOS track/hold circuit | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems | 3 | | 1709 | 1712 | 1999 | https://doi.org/10.1109/ICECS.1999.8145051 | Refereed |
